Κανονική προβολή Προβολή MARC Προβολή ISBD

Computer - Aided Designs Tools for Digital Systems TUTORIAL. A tutorial on design automation tools at the architecture and register - transfer level W. M. vanCleemput

Συντελεστής(ές): Τύπος υλικού: ΚείμενοΚείμενοΛεπτομέρειες δημοσίευσης: New York The Institute of Electrical and Electronic Engineers, Inc. c1979Έκδοση: 2nd edΠεριγραφή: v, 168 p., figΘέμα(τα): Ταξινόμηση DDC:
  • 621.381 5 21h
Ελλιπή περιεχόμενα:
Preface Part 1: Introduction The Role of Design Automation in the Design of Digital Systems A Structured Design Automation Environment for Digital Systems Part II : Design Languages A Survey of Computer Hardware Description Language in the USA Introducing PMS An Hierarchical Language for the Structural Description of Digital Systems SCALD:Structured Computer-Aided Logic Design An Architectural Research Facility - ISP Descriptions, Simulation, Data Collection Introducing CDL/ Yaohan Chu Introducing CDL /D.L. Dietmeyer Introducing AHPL / Frederick J. Hill Part III : System Level Description LOGOS and the Software Engineer Modeling for Syntesis - The Gap Between Intent and Behavior State of the Implementation of SARA Multi-Level Modeling in SARA The Graph Model of Behavior Simulator Developing a SARA Building Block - The 8080 Specialization of SARA for Software Synthesis Part IV : System Level Simulation Computer System Simulation : An Introduction Part V : Register Transfer and Gate Level Simulation Design Verification at the Register Transfer Language Level Digital Logic Simulation In a Time - Based, Table - Driven Environment. Part 1. Design Verification Digital Logic Simulation In a Time-Based, Table-Driven Environment. Part 2. Parallel Fault Simulation

Περιέχει Βιβλιογραφικές Αναφορές

Preface Part 1: Introduction The Role of Design Automation in the Design of Digital Systems A Structured Design Automation Environment for Digital Systems Part II : Design Languages A Survey of Computer Hardware Description Language in the USA Introducing PMS An Hierarchical Language for the Structural Description of Digital Systems SCALD:Structured Computer-Aided Logic Design An Architectural Research Facility - ISP Descriptions, Simulation, Data Collection Introducing CDL/ Yaohan Chu Introducing CDL /D.L. Dietmeyer Introducing AHPL / Frederick J. Hill Part III : System Level Description LOGOS and the Software Engineer Modeling for Syntesis - The Gap Between Intent and Behavior State of the Implementation of SARA Multi-Level Modeling in SARA The Graph Model of Behavior Simulator Developing a SARA Building Block - The 8080 Specialization of SARA for Software Synthesis Part IV : System Level Simulation Computer System Simulation : An Introduction Part V : Register Transfer and Gate Level Simulation Design Verification at the Register Transfer Language Level Digital Logic Simulation In a Time - Based, Table - Driven Environment. Part 1. Design Verification Digital Logic Simulation In a Time-Based, Table-Driven Environment. Part 2. Parallel Fault Simulation

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