Στοιχεία MARC
| 000 -LEADER |
|---|
| fixed length control field |
01524nam a2200277 u 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
10107003 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
upatras |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210914113227.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
040624s |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
1558605576 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.381 52 SUT |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Logical Effort |
| Remainder of title |
Designing Fast CMOS Circuits |
| Statement of responsibility, etc. |
Ivan Sutherland, Bob Sproull, David Harris |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc. |
San Francisco |
| Name of publisher, distributor, etc. |
Morgan Kaufmann Publishers |
| Date of publication, distribution, etc. |
c1999 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
viii,239p. |
| Other physical details |
fig.,tabl. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
βιβλιογραφία : σ. 233, ευρετήριο : σσ. 235 - 239, περιέχει ασκήσεις ανα κεφάλαιο. |
| 505 1# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Contents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Λογικός σχεδιασμός |
| 9 (RLIN) |
128003 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
CMOS |
| 9 (RLIN) |
113287 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
CMOS CIRCUITS |
| 9 (RLIN) |
127742 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
DELAY FAULTS (SEMICONDUCTORS) |
| 9 (RLIN) |
127743 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
SUTHERLAND, IVAN |
| Relator code |
aut |
| 9 (RLIN) |
127744 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
SPROULL, Bob |
| Relator code |
aut |
| 9 (RLIN) |
127745 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Harris, David Money |
| Relator code |
aut |
| 9 (RLIN) |
127746 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
