Logical Effort
Logical Effort Designing Fast CMOS Circuits
Ivan Sutherland, Bob Sproull, David Harris
- San Francisco Morgan Kaufmann Publishers c1999
- viii,239p. fig.,tabl.
βιβλιογραφία : σ. 233, ευρετήριο : σσ. 235 - 239, περιέχει ασκήσεις ανα κεφάλαιο.
Contents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index
1558605576
Λογικός σχεδιασμός
CMOS
CMOS CIRCUITS
DELAY FAULTS (SEMICONDUCTORS)
621.381 52 SUT
βιβλιογραφία : σ. 233, ευρετήριο : σσ. 235 - 239, περιέχει ασκήσεις ανα κεφάλαιο.
Contents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index
1558605576
Λογικός σχεδιασμός
CMOS
CMOS CIRCUITS
DELAY FAULTS (SEMICONDUCTORS)
621.381 52 SUT
