| 000 | 01524nam a2200277 u 4500 | ||
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| 001 | 10107003 | ||
| 003 | upatras | ||
| 005 | 20210914113227.0 | ||
| 008 | 040624s | ||
| 020 | _a1558605576 | ||
| 082 | 0 | 4 | _a621.381 52 SUT |
| 245 | 1 | 0 |
_aLogical Effort _bDesigning Fast CMOS Circuits _cIvan Sutherland, Bob Sproull, David Harris |
| 260 |
_aSan Francisco _bMorgan Kaufmann Publishers _cc1999 |
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| 300 |
_aviii,239p. _bfig.,tabl. |
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| 504 | _aβιβλιογραφία : σ. 233, ευρετήριο : σσ. 235 - 239, περιέχει ασκήσεις ανα κεφάλαιο. | ||
| 505 | 1 | _aContents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index | |
| 650 | 4 |
_aΛογικός σχεδιασμός _9128003 |
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| 650 | 4 |
_aCMOS _9113287 |
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| 650 | 4 |
_aCMOS CIRCUITS _9127742 |
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| 650 | 4 |
_aDELAY FAULTS (SEMICONDUCTORS) _9127743 |
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| 700 | 1 |
_aSUTHERLAND, IVAN _4aut _9127744 |
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| 700 | 1 |
_aSPROULL, Bob _4aut _9127745 |
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| 700 | 1 |
_aHarris, David Money _4aut _9127746 |
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| 942 | _2ddc | ||
| 999 |
_c93017 _d93017 |
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