| 000 | 00886nam a2200265 u 4500 | ||
|---|---|---|---|
| 001 | 10105482 | ||
| 003 | upatras | ||
| 005 | 20210117204158.0 | ||
| 008 | 991213s1990 f eng | ||
| 020 | _a0 7923 9058 X | ||
| 040 |
_aΒιβλιοθήκη ΙΤΥ _cΒιβλιοθήκη ΙΤΥ |
||
| 040 |
_aXX-XxUND _cΒιβλιοθήκη ΙΤΥ |
||
| 082 | 1 | 4 |
_a621.395 _220th ed. |
| 245 | 1 | 0 |
_aHierarchical Modeling for VLSI Circuit Testing _cDebashis Bhattacharya, John P. Hayes authors |
| 260 |
_aBoston _bKluwer Academic Publishers _c1990 |
||
| 300 | _cx,159p.:fig. | ||
| 650 | 4 |
_aΕΠΕΑΕΚ _9116438 |
|
| 650 | 4 |
_aVLSI _924366 |
|
| 650 | 4 |
_aINTEGRATED CIRCUITS _924300 |
|
| 650 | 4 |
_aCOMPUTER SIMULATION _924424 |
|
| 700 | 1 |
_aBhattacharya, Debashis _9124675 |
|
| 700 | 1 |
_aHayes, John P. _9105528 |
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| 942 | _2ddc | ||
| 999 |
_c90064 _d90064 |
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