Computer Architecture (Αριθ. εγγραφής 92703)

Στοιχεία MARC
000 -LEADER
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001 - CONTROL NUMBER
control field 10106842
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control field upatras
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20210117204321.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 030408s gre
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0 89791 101 6
040 ## - CATALOGING SOURCE
Original cataloging agency Βιβλιοθήκη ΕΑΙΤΥ
Transcribing agency Βιβλιοθήκη ΕΑΙΤΥ
040 ## - CATALOGING SOURCE
Original cataloging agency XX-XxUND
Transcribing agency Βιβλιοθήκη ΕΑΙΤΥ
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004.22
245 10 - TITLE STATEMENT
Title Computer Architecture
Remainder of title Conference Proceedings of the 10th Annual International Symposium June 13-17, 1983. ACM SIGARCH NEWSLETTER: Vol. 11, No. 3, 1983
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. New York
Name of publisher, distributor, etc. IEEE Computer Society Press
Date of publication, distribution, etc. 1983
300 ## - PHYSICAL DESCRIPTION
Extent ix, 438 p., fig.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc Includes bibliography, Author Index pp. 437-438
505 1# - FORMATTED CONTENTS NOTE
Formatted contents note Session 1 : Introduction and Keynote Speech
-- Size, Power, and Speed
-- Session 2 : Computer Architecture Taxonomy
-- Towards a Taxonomy of Computer Architecture Based on thw Machine Data Type View
-- Framework for a Taxonomy of Fault - Tolerance Attributes in Computer Systems
-- Session 3 : Architecture Design Methods
-- Caddie - An Interactive Design Environment
-- On the Verification of Computer Architecture Using an Architecture Description Language
-- Research on Synthesis of Concurrent Computing Systems
-- Session 4 : VLSI Architectures
-- Architecture of the PSC : A programmable Systolic Chip
-- Synchronizing Large VLSI Processor Arrays
-- The Boolean Vector Machine
-- A VLSI Area Machine for Relational Data Bases
-- Session 5A : Data Flow Architecture I
-- Implementing Streams on a Data Flow Computer System with Paged Memory
-- The Piecewise Data Flow Architecture Control Flow and Register Management
-- On the Working Set Concept for Data - Flow Machines
-- A Data Driven System Based on a Microprogrammed Processor Module
-- Session 5B : Cache Memories
-- Architecture of a VLSI Instruction Cache for a RISC
-- Performance of Shared Cache for Parallel - Pipelined Computer Systems
-- Using Cache Memory to Reduce Processor - Memory Traffic
-- A Study of Instruction Cache Organizations and Replacement Policies
-- Section 6A : Multiple Functional Unit Processors
-- Very Long Instruction Word Architectures and the ELI -512
-- A User - Microprogrammable, Local Host Computer with Low-Level Parallelismk
-- Session 6B : Reliability
-- Combining Tags with Error Codes
-- Fault Diagnosis of Bit - Splice Processor
-- Section 7A : Interconnection Networka I
-- Line Digraph Interations and the (d, k) Problem for Directed Graphs
-- Resourcw Allocation in Rectangular CC-Banyans
-- Uniform Theory of the Shuffle-Exchange Type Permutation Networks
-- Section 7B : Performance Evaluation of Scientific Computers
-- Analysis of Gray - 1S Architecture
-- Performance Measurements on HEP - A Pipelined MIMD Computer
-- (SM)2 : Sparse matrix Solving Machine
-- Session 8: Educational Aspects of Computer Architecture
-- An Experimental System for Computer Science Instruction
-- Session 9A : Data Flow Architectures II
-- Execution Control and Memory Science Instruction
-- DDDP : A DIstibuted Data Driven Processor
-- A Data Flow Processor Array System : Design and Anlysis
-- Session 9B : processor and I/O Architectures
-- A Restospective on the Dorado, A High - Performance Personal Computer
-- System / 370 Extended Architecture : A Program View of the Channel Subsystem
-- Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
-- Session 10A : Interconnection Networks II
-- Switching Strategies in a Class of Packet Switching Networks
-- A Comparative Study of Distributed Resource Sharing on Multiprocessors
-- Concurrent Error Detection in VLSI Interconnection Networks
-- Session 10B : Multicomputers and Multiprocessors
-- Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures
-- EMMA : An Industrial Experience on Large Multiprocessing Architectures
-- A Communication Structure for a Multiprocessor Computer with Distributed Global Memory
-- Session 11A : Architectural Support for High Level Languages
-- ALPHA : A High - Performance LISP Machine Equipped with a New Stack Structure and Carbage Collection System
-- A Parallel Execution Model of Logic Programs
-- A System Architecture for the Concurrent Evaluation of Applicative Program Expressions
-- A Performance Evaluation of a Lisp - Based Data -Driven Machine (EM3)
-- Session 11B : Architectures for Image Processing
-- A Pyramidal Approach to Parallel Processing
-- The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach
-- LINKS-1 : A Parallel Pipelined Multimicrocomputer System for Image Creation
-- LIPP - A SIMD Multiprocessor Architecture for Image Processing
-- Special Day : Applied Artificial Intelligence and Its Influence on Computer Architecture
-- The New Generation of Computer Architecture
-- Inference Machine
-- Overview to the Fifth Generation Computer System Project
-- A Relational Data Base Machine : First Step to Knowledge Base Machine
-- A Critique of Multiprocessing von Neumann Style
-- Author Index
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element ACM
9 (RLIN) 24250
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element COMPUTER ARCHITECTURE
9 (RLIN) 24451
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element IEEE
9 (RLIN) 24256
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element SIGARCH
9 (RLIN) 24452
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element PROCEEDINGS
9 (RLIN) 24278
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element ΠΡΑΚΤΙΚΑ ΣΥΝΕΔΡΙΩΝ
9 (RLIN) 113060
650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element ΓΑΛΛΟΠΟΥΛΟΣ
9 (RLIN) 113813
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element IEEE Computer Society
Relator code fnd
9 (RLIN) 23536
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element Association for Computing Machinery
Relator code fnd
9 (RLIN) 24263
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
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