Hierarchical Modeling for VLSI Circuit Testing
Hierarchical Modeling for VLSI Circuit Testing
Debashis Bhattacharya, John P. Hayes authors
- Boston Kluwer Academic Publishers 1990
- x,159p.:fig.
0 7923 9058 X
ΕΠΕΑΕΚ
VLSI
INTEGRATED CIRCUITS
COMPUTER SIMULATION
621.395
0 7923 9058 X
ΕΠΕΑΕΚ
VLSI
INTEGRATED CIRCUITS
COMPUTER SIMULATION
621.395